SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. The new standard will include design specification methods, embedded assertions language, test bench language including coverage and assertions API, and a direct programming interface. The proposed SystemVerilog standard enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows. The purpose of this project is to provide the EDA, Semiconductor, and System Design communities with a well-defined and official IEEE Unified Hardware Design, Specification and Verification standard language. The language is designed to co-exist and enhance those hardware description languages presently used by designers while providing the capabilities lacking in those languages. New IEEE Standard - Superseded. This standard represents a merger of two previous standards: IEEE 1364-2005 Verilog hardware description language (HDL) and IEEE 1800-2005 SystemVerilog unified hardware design, specification and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard enables users to have all information regarding syntax and semantics in a single document. (Adopted as IEC 62530:2007)