This document gives guidance on VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. The method is applicable for PBTI testing, NBTI and threshold voltage changes caused by switching events are excluded from the scope.

SiC MOSFETs have threshold voltage hysteresis caused by transient trap effects, which impacts the evaluation of the actual the VT shift caused by stress tests such as bias temperature instabilities (BTI) [2].

The test methods can be applied to the following:
a) N-channel SiC MOSFET (vertical structure);
b) the above in wafer and package levels.