IEC 62530 Ed. 1.0 en:2007
Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
International Electrotechnical Commission , 11/07/2007
$174.00
$347.00
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
Product Information
Published:
11/07/2007
Pages:
663
File Size:
1 file , 6.9 MB
Language:
English
Note:
This product is unavailable in Ukraine, Russia, Belarus
IEC 62530 Ed. 3.0 en:2021
$256.00
IEC 62530 Ed. 2.0 en:2011
$222.00
IEC 62530 Ed. 1.0 en:2007
$174.00
Related Documents
IEC 60728-7-1 Ed. 1.1 b:2015
$101.00
IEC 61274-1 Ed. 2.0 b:2007
$73.00
IEC 61347-2-8 Ed. 1.1 b:2006
$114.00
