Structures are defined in STIL to support usage as semiconductor simulation stimulus, including the following: a) Mapping signal names to equivalent design references b) Interface between scan and built-in self test (BIST) and the logic simulation c) Data types to represent unresolved states in a pattern d) Parallel or asynchronous pattern execution on different design blocks e) Expression-based conditional execution of pattern constructs Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test. Structures are defined in STIL to relate fail information from device testing environments back to original stimulus and design data elements.